A Systematic Approach to Optimizing and Verifying Synthesized High-Speed ASICs
نویسندگان
چکیده
This paper describes the design process used in developing a Stream Memory Controller (SMC)*. The SMC can reorder processor-memory accesses dynamically to increase the effective memory bandwidth for vector operations. A 132-pin ASIC was implemented in static CMOS using a 0.75μm process and has been tested at 36MHz. * This work was sponsored by the National Science Foundation under Grant MIP-9307626.
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